module emitter(
  input        io_systemclk,
  input        io_systemRstn,
  input        io_enable,
  input  [1:0] io_emitterio_fpga_cim_data,
  input        io_emitterio_fpga_cim_cmd,
  output       io_emitterio_cim_fpga_state,
  output [7:0] io_emitterio_cim_fpga_result,
  output [1:0] io_chipio_fpga_cim_data,
  output       io_chipio_fpga_cim_cmd,
  input        io_chipio_cim_fpga_state,
  input        io_chipio_cim_fpga_clk,
  input  [7:0] io_chipio_cim_fpga_result
);
  wire  BUFG_I; // @[emitter.scala 41:22]
  wire  BUFG_O; // @[emitter.scala 41:22]
  wire  systemRst = ~io_systemRstn; // @[emitter.scala 34:19]
  reg [1:0] data; // @[Reg.scala 28:20]
  reg  cmd; // @[Reg.scala 28:20]
  reg  state; // @[Reg.scala 28:20]
  reg [7:0] result; // @[Reg.scala 28:20]
  BUFG BUFG ( // @[emitter.scala 41:22]
    .I(BUFG_I),
    .O(BUFG_O)
  );
  assign io_emitterio_cim_fpga_state = state; // @[emitter.scala 46:35]
  assign io_emitterio_cim_fpga_result = result; // @[emitter.scala 47:35]
  assign io_chipio_fpga_cim_data = data; // @[emitter.scala 38:33]
  assign io_chipio_fpga_cim_cmd = cmd; // @[emitter.scala 39:33]
  assign BUFG_I = io_chipio_cim_fpga_clk; // @[emitter.scala 42:12]
  always @(posedge io_systemclk) begin
    if (systemRst) begin // @[Reg.scala 28:20]
      data <= 2'h0; // @[Reg.scala 28:20]
    end else if (io_enable) begin // @[Reg.scala 29:18]
      data <= io_emitterio_fpga_cim_data; // @[Reg.scala 29:22]
    end
    if (systemRst) begin // @[Reg.scala 28:20]
      cmd <= 1'h0; // @[Reg.scala 28:20]
    end else if (io_enable) begin // @[Reg.scala 29:18]
      cmd <= io_emitterio_fpga_cim_cmd; // @[Reg.scala 29:22]
    end
  end
  always @(posedge BUFG_O) begin
    if (systemRst) begin // @[Reg.scala 28:20]
      state <= 1'h0; // @[Reg.scala 28:20]
    end else if (io_enable) begin // @[Reg.scala 29:18]
      state <= io_chipio_cim_fpga_state; // @[Reg.scala 29:22]
    end
    if (systemRst) begin // @[Reg.scala 28:20]
      result <= 8'h0; // @[Reg.scala 28:20]
    end else if (io_enable) begin // @[Reg.scala 29:18]
      result <= io_chipio_cim_fpga_result; // @[Reg.scala 29:22]
    end
  end
endmodule
